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MC54/74F109 DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
The MC54/74F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to F74 data sheet) by connecting the J and K inputs together.
DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP
FASTTM SCHOTTKY TTL
CONNECTION DIAGRAM
VCC CD2 16 15 CD CD1 J1 1 CD1 2 J1 J2 14 J K2 13 K CP2 SD2 11 12 CP SD Q2 10 Q Q Q1 7 Q1 8 GND
16 1 16 1
Q2 9
K1 3 K1
CP1 SD1 4 5
Q1 6 Q1
J SUFFIX CERAMIC CASE 620-09
CP1 SD1
N SUFFIX PLASTIC CASE 648-08
FUNCTION TABLE (Each Half)
Input @ tn J L L H H
Asynchronous Inputs: LOW Input to SD sets Q to HIGH level LOW Input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH H = HIGH Voltage Level L = LOW Voltage Level tn = Bit time before clock pulse tn + 1 = Bit time after clock pulse
Output @ tn + 1 Q Q
16 1
K H L H L
D SUFFIX SOIC CASE 751B-03
No Change L H H L
ORDERING INFORMATION
MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC
Toggles
LOGIC SYMBOL
5 2 4 3 J SD Q J
11 SD Q
6
14 12
10
CP KC Q D 1 7
CP K CD 15 Q 9
13
VCC = PIN 16 GND = PIN 8
FAST AND LS TTL DATA 4-42
MC54/74F109
LOGIC DIAGRAM (one half shown)
Q
Q
K J CP SD CD
NOTE: This diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
GUARANTEED OPERATING RANGES
Symbol VCC TA Supply Voltage Operating Ambient Temperature Range Parameter 54, 74 54 54 IOH IOL Output Current -- High Output Current -- Low 54, 74 54, 74 Min 4.5 -55 0 Typ 5.0 25 25 Max 5.5 125 70 -1.0 20 mA mA Unit V C
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 54, 74 74 VOL IIH Output LOW Voltage Input HIGH Current 2.5 2.7 3.4 3.4 0.35 0.5 20 100 IIL Input LOW Current (J, K and CP Inputs) (CD and SD Inputs) IOS ICC Output Short Circuit Current (Note 2) Power Supply Current -60 11.7 -0.6 -1.8 -150 17 Min 2.0 0.8 -1.2 Typ Max Unit V V V V V V A A mA mA mA mA VOUT = 0 V VCP = 0 V VCC = MAX VCC = MAX Test Conditions Guaranteed Input HIGH Voltage Guaranteed Input LOW Voltage IIN = -18 mA IOH = -1.0 mA IOH = -1.0 mA IOL = 20 mA VIN = 2.7 V VIN = 7.0 V VIN = 0.5 V VCC = MAX VCC = MIN VCC = 4.50 V VCC = 4.75 V VCC = MIN VCC = MAX
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under guaranteed operating ranges. 2. Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA 4-43
MC54/74F109
AC CHARACTERISTICS
54/74F TA = +25C VCC = +5.0 V CL = 50 PF Symbol fmax tPLH tPHL tPLH tPHL Parameter Maximum Clock Frequency Propagation Delay CPn to Qn or Qn Propagation Delay CDn or SDn to Qn or Qn Min 100 3.8 4.4 2.5 3.5 Typ 125 5.3 6.2 5.2 7.0 7.0 8.0 7.0 9.0 Max 54F TA = -55C to +125C VCC = 5.0 V 10% CL = 50 PF Min 70 3.8 4.4 2.5 3.5 9.0 10.5 9.0 11.5 Max 74F TA = 0C to +70C VCC = 5.0 V 10% CL = 50 PF Min 90 3.8 4.4 2.5 3.5 8.0 ns 9.2 8.0 ns 10.5 Max Unit MHz
AC OPERATING REQUIREMENTS
54/74F TA = +25C VCC = +5.0 V Symbol ts(H) ts(L) th(H) th(L) tw(H) tw(L) tw(L) trec Parameter Setup Time, HIGH or LOW Jn or Kn to CPn Hold Time, HIGH or LOW Jn or Kn to CPn CPn Pulse Width, HIGH or LOW CDn or SDn Pulse Width, LOW Recovery Time CDn or SDn to CP Min 3.0 3.0 1.0 1.0 4.0 5.0 4.0 2.0 Typ Max 54F TA = -55C to +125C VCC = 5.0 V 10% Min 3.0 3.0 1.0 1.0 4.0 5.0 4.0 2.0 Max 74F TA = 0C to +70C VCC = 5.0 V 10% Min 3.0 3.0 ns 1.0 1.0 4.0 ns 5.0 4.0 2.0 ns ns Max Unit
FAST AND LS TTL DATA 4-44

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